The production of integrated circuits begins with the creation of high-quality semiconductor wafers. During the wafer fabrication process, the wafers may undergo multiple masking, etching, and dielectric and conductor deposition processes. In addition, metallization, which generally refers to the materials, methods and processes of wiring together or interconnecting the component parts of an integrated circuit located on the surface of a wafer, is critical to the operation of a semiconductor device. Typically, the “wiring” of an integrated circuit involves etching trenches and “vias” in a planar dielectric (insulator) layer and filling the trenches and vias with a conductive material, typically a metal.
In the past, aluminum was used extensively as a metallization material in semiconductor fabrication due to the leakage and adhesion problems experienced with the use of gold. Other metallization materials have included Ni, Ta, Ti, W, Ag, Cu/Al, TaN, TiN, CoWP, NiP and CoP.
Recently, techniques have been developed which utilize copper to form conductive features because copper is less susceptible to electromigration and exhibits a lower resistivity than aluminum. Since copper does not readily form volatile or soluble compounds, the copper conductive features are often formed using damascene processes. Generally, the copper conductive features are formed by creating a via within an insulating material, depositing a barrier layer onto the surface of the insulating material and into the via, depositing a seed layer of copper into the barrier layer, and electrodepositing a copper layer onto the seed layer to fill the via.
As the size of integrated circuits continues to decrease and the density of microstructures on integrated circuits increases, the need for precise wafer surfaces becomes more important. However, substantially planar deposition of copper is difficult in ULSI chip processing, especially when the feature sizes are about 2 μm wide and larger. To fill such wide features, it is often necessary to deposit relatively thick layers, typically 700 nm and greater over the rest of the work piece. A subsequent planarization process then is required to remove the thick excess deposition metal layers and to level the surface needed for further integrated circuit manufacturing. Such planarization processes typically include a chemical mechanical planarization process, which mechanically removes the thick excess metal layer, or a reverse polarity deposition process, which electrically removes the thick excess metal layer. Deposition of such thick layers of metal followed by a planarization process to subsequently remove the thick excess metal layer increases the costs of the electrodeposition process and decreases throughput.
Accordingly, it is desirable to provide a new composition and method for electrodeposition of a metal on a work piece. It is also desirable to provide a composition and method for electrodeposition of a substantially planar metal film on a work piece. It is further desirable to provide a composition and method for electrodeposition of a thin metal film on a work piece. Other desirable features and characteristics of the present invention will become apparent from the subsequent description and the appended claims, taken in conjunction with the accompanying drawings.